1. Field of the Invention
The present invention relates to a buffer device used when transmitting data.
2. Description of the Related Art
When transmitting data from a system on a transmitting side to a system on a receiving side, there are cases when buffers are provided between the two systems and cases when they are not. FIG. 1 illustrates a case in which data is transmitted without the use of a buffer.
In FIG. 1, a transmission-side data bus 401 and a reception-side data bus 402 are directly connected, and in addition to these data buses, there is provided a signal line 403 from the reception side to the transmission side. The signal line 403 is provided for the purpose of transferring to the transmission side a reception-ready signal indicated that the reception side is in a state capable of reception. The transmission side then checks the reception-ready signal and sends the data to the reception side. If the transmission side is unable to confirm the signal, it suspends transmission until it receives the signal. This type of control is performed because transmitted data is lost when the reception side is not in a reception-ready state. In this method, the transmission side and reception side are directly connected and secure transmission of data can therefore be performed. However, when the two sides differ greatly in transmission speed, waiting time will be generated on the side capable of faster transmission and transmission efficiency is poor.
Here, an improvement in transmission efficiency can be sought by providing a First-In First-Out (FIFO) buffer between the transmission side and reception side. FIG. 2 is a block diagram illustrating a conventional data transmission device using an FIFO buffer.
In FIG. 2, an FIFO device 301 is provided between the data bus 302 of the transmission-side terminal and the data bus 304 of the reception-side terminal. The transmission side apparatus is connected in order to transmit data to the FIFO device 301, and the FIFO device 301 is connected in order to transmit data to the reception side apparatus.
Inside the FIFO device 301 are provided a number n of buffers b.sub.1, b.sub.2, . . . , b.sub.n in a series. The first buffer b.sub.1 is directly connected to the transmission side, and the n.sup.th buffer b.sub.n is directly connected to the reception side. The second buffer b.sub.2 is the next buffer after buffer b.sub.1. Each of the buffers b.sub.1 to b.sub.n is composed of write attribute bits w.sub.1 to w.sub.n and data holders d.sub.1 to d.sub.n that actually hold data. Write attribute bits w.sub.1 to w.sub.n are flags that indicate the presence or absence of data in the corresponding data holders d.sub.1 to d.sub.n, "0" indicating an absence of data and "1" indicating that data is being held. The first buffer b.sub.1 transmits data to the second buffer b.sub.2, and the following buffers proceed similarly, the m.sup.th buffer b.sub.m transmitting data to the [m+1].sup.th buffer b.sub.m+1. A signal line 306 is provided for the purpose of inputting from the reception side to the FIFO device 301 a reception-ready signal, and another signal line 305 is provided for providing from the FIFO device 301 to the transmission side a reception-ready signal for the FIFO device 301 itself. In addition, there is provided in the FIFO device a reset signal line 303 for the purpose of forcibly setting all of the write attribute bits w.sub.1 to w.sub.n to "0. "
The transmission side, after receiving the reception-ready signal from the FIFO device 301, confirms that the first buffer b.sub.1 within the FIFO device 301 is empty, and then transmits data to the FIFO device 301. At this time, as a flag indicating that data is present, "1" is entered to the write attribute bit w.sub.1 corresponding to the data holder d.sub.1 into which data has been transmitted.
Within the FIFO device 301, if the second buffer b.sub.2 is empty, data is moved to the second buffer b.sub.2 and the first buffer b.sub.1 becomes empty. At this time, as a flag indicating that data is absent, "0" is entered to the write attribute bit w.sub.1 of the sending source buffer b.sub.1. By the same process, this operation is repeated until the n.sup.th buffer b.sub.n. The presence or absence of data within each buffer b.sub.1 to b.sub.n is checked by means of the write attribute bits w.sub.1 to w.sub.n. The n.sup.th buffer b.sub.n confirms that the reception side is in a reception-ready state. When a reception-ready signal is received from signal line 306, data is transmitted to the reception side.
When this type of FIFO device 301 is interposed between a transmission side and a reception side, data can be transmitted by the same operations as viewed by the either the transmission side or the reception side as in the previously-described case in which a buffer is not used. Furthermore, if an FIFO device having high-speed and sufficient data capacity is used, the transmission side considers itself connected with a high-speed reception terminal while the reception side takes in data according to its own reception speed, and as a result, waiting time can be reduced without such problems as loss of data, and a real increase in transmission efficiency can be achieved.
However, if this type of FIFO device is applied in a circuit that can be disconnected from the reception side during data transmission, data transmission efficiency may suffer due to data resending that accompanies circuit disconnection. As an example of the sort of circuit that can be disconnected from the reception side, there is a packet circuit that uses a D-channel at the S-interface of an ISDN (Integrated Services Digital Network). When resending data, because the meaning carried by the data will change according to its sequence of transmission, the data must be transmitted again beginning from its start. The data that has already been transmitted to the FIFO device must therefore be completely erased by means of a reset signal and all of the data must be sent again by way of the FIFO device. Ultimately, if data resending is carried out, all of the data must again be transmitted as in a case in which a buffer is not provided, and as a result, the amount of outgoing data increases, the transmission efficiency drops, and the advantages of using an FIFO device are lost.